1. Field of the Invention
The present invention relates to a logic circuit model conversion apparatus and a method thereof; and a logic circuit model conversion program.
2. Description of the Related Art
The design/manufacture of a large scale logic circuit such as an LSI is often carried out as follows. Hardware is described in a language called Hardware Description Language (hereinafter, referred to as “HDL”). The described HDL is converted into data indicating connection relationship between circuit elements called “net list”. Then, hardware such as an actual LSI is manufactured from this net list.
Converting the HDL into a net list is called “logical synthesis”, and the HDL can be converted into the net list by using a predetermined logic synthesis tool. The net list is data representing a mutual connectivity with a circuit element such as an AND circuit, an OR circuit, a register, or a counter, for example. By using the net list, a so called circuit diagram that exists conventionally can be printed out.
There are a variety of HDLs, and, for example, the HDLs such as Verilog-HDL, VHDL, and System C are often used today. In addition, in the HDLs, some description levels exist, and typically, there are a Behavior Level and a Register Transfer Level (hereinafter, referred to as “RTL”).
The Behavior Level is a level at which an operation (including a software operation in addition to a hardware operation) is represented without “concept of clock”. This level is used for description of a circuit block in which detailed design specification is not defined or description of a model provided for the purpose of simulation, for example, description of a modeled CPU operation.
In contrast, the RTL is a level of expressing a register, a counter and the like that are constituent circuit elements and a transfer state (connection state) of data between them. At this level, “concept of clock” for operating these constituent elements exists.
In order to “logically synthesize” an HDL and generate a net list, it is necessary to describe the HDL in the RTL. A logic circuit described in the HDL at the RTL level is referred to as a “logic circuit RTL model”.
On the other hand, in a large-scale circuit today, in addition to a design of the circuit itself, verification and evaluation of the designed circuit becomes very important. Sufficient verification and evaluation are carried out at a design stage (before producing a material). As a result, a development period is shortened, and a development cost can be reduced.
Further, in many of the systems today, hardware/software integrated systems including microprocessors or the like becomes common. Thus, there is a growing need for verification and evaluating software operated by microprocessors or the like as well as verification and evaluating hardware.
In the meantime, a logic circuit widely used today is a synchronous logic circuit. In a “logic circuit RTL model”, a description is given so as to carry out writing into a defined register group by using a sync signal such as clock and reset. Therefore, time-based accuracy that can be evaluated in the “logic circuit RTL model” is accuracy that can be guaranteed to enable verification as to whether or not a register value is correct every time a sync signal such as a cyclic clock is inputted (hereinafter, referred to as “clock cycle accuracy”). In this manner, the verification using the “logic circuit RTL model” enables very strict verification for every clock cycle.
However, in a large-scale logic circuit including microprocessors or the like, when individual logic circuits or software components communicating with these circuits and operating on microprocessors are verified with clock cycle accuracy by using a simulation environment in which the “logic circuit RTL model” and the simulator of the microprocessors are connected to each other, a simulation time becomes very long.
On the other hand, in the case of software verification such as microprocessors communicating with the “logic circuit RTL model”, it is not always necessary to verify with fine accuracy such as clock cycle accuracy. In addition, it is not necessary to fully monitor and verify the states of internal registers in the “logic circuit RTL model”.
Therefore, there have been developed a variety of techniques of lowering the time accuracy of simulation (time-based monitoring and verifying roughness) or spatial accuracy (type or quantity of register or signal to be monitored or verified) in a range for achieving a verification purpose, thereby shortening a simulation time.
For example, in the U.S. Pat. No. 5,862,361, there is disclosed a technique of creating a table with respect to times of clock cycles by utilizing features of a synchronous circuit, and then, carrying out event scheduling before carrying out simulation.
As described above, a model for carrying out simulation (hereinafter, this model is referred to as a “logic circuit operation model”) is often generated in accordance with a method of newly generating models each having a high degree of abstraction other than the “logic circuit RTL model”, and then, sequentially detailing these models to generate the “logic circuit operation model” or in accordance with a method of using the existing “logic circuit RTL model (model having a low degree of abstraction and having fineness) to summarize the model, thereby converting the summarized model into a “logic circuit operation model”.
It is necessary to judge whether or not the “logic circuit operation model” is proper from the three points of view: the accuracy of the “logic circuit operation model” (first condition); what it takes to create the “logic circuit operation model” (second condition); and speed of implementing the logic circuit operation model (third condition).
The accuracy of the “logic circuit operation model” (first condition) is to allocate simulation accuracy (time-based accuracy and spatial accuracy) sufficient to achieve a verification purpose.
What it takes to create the “logic circuit operation model” (second condition) is that the “logic circuit operation model” is provided in a state in which the “logic circuit operation model” coincides with the “logic circuit RTL model” by the time verification of a logic circuit or a software program starts.
The speed of implementing the “logic circuit operation model” (third condition) is to include a speed of executing simulation for the purpose of verification within a sufficiently short time with respect to a period from the beginning to a period of starting verification of the logic circuit or software program.
For example, in the above described method of summarizing a model having fine simulation accuracy (low degree of abstraction) (Refer to U.S. Pat. No. 5,862,361), there is a comparatively high possibility of meeting the first and second condition (development inconvenience) because the “logic circuit operation model” is created while automatic summarization is carried out with the designed “logic circuit RTL model” being a start point. However, this method is not sufficiently fast on an aspect of the implementation speed, and does not meet the third condition.
Therefore, in a conventional technique, it is thought difficult to obtain a “logic circuit operation model” that meets the third condition in which, in a development period to an extent such that while the accuracy of meeting the first condition is maintained, the second condition is met, a simulation implementing time is included in a practically endurable range even in a large-scale system.